Intel's ACE brings outer-product matrix math to x86, rivaling Arm SME
Intel's ACE extends AMX with outer-product matrix acceleration, compared against Arm's SME2 in a detailed technical breakdown.
The x86 Ecosystem Advisory Group has published a whitepaper and specification for ACE, a second accelerator type built on Intel's AMX extension. Unlike the original TMUL accelerator introduced with Sapphire Rapids, ACE fixes tile registers at 64 bytes by 16 rows, drops complex number support, and adds FP8. More significantly, it shifts from inner-product to outer-product matrix multiplication — the same approach Arm's SME/SME2 extension takes.
This isn't a coincidental design choice: most linear algebra operations, including matrix multiplication, can be expressed as sums of outer products, reducing the register state software needs to track. ACE also leans on AVX-512's fixed 512-bit vector width to accelerate dequantization of model weights, using a new VUNPACKB instruction alongside VPERMB/VPERMI2B to handle any data type from 2 to 7 bits — offering flexibility for future quantization schemes.
Arm's SME2 instead uses a fixed-width 512-bit ZT0 lookup-table register, with LUTI2/LUTI4 instructions performing 2-bit or 4-bit conversions without needing an intermediate unpacking register. However, it can't match ACE's coverage of the full 2-to-7-bit range or support complex codebook schemes requiring multiple lookup tables. For engineers working on ML inference acceleration, the comparison highlights how x86 and Arm are diverging architecturally even while converging on the same mathematical primitive.