AMD Epyc 9996 'Venice': 256-core Zen 6 chip claims 3.4x lead over Xeon
AMD's 256-core Epyc 9996 Venice Zen 6 chip claims up to 3.4x throughput over Intel Xeon 6980P and 2.2x over Nvidia Vera in early benchmarks.
AMD has detailed its first Zen 6 server chip, the Epyc 9996 "Venice," a 256-core/512-thread part built on TSMC N2 using the dense Zen 6c design with 32 cores per CCD and two IODs. The chip carries 1,024MB of L3 cache (non-stacked), 16-channel memory support up to 12,800 MT/s MRDIMMs for 1.6TB/s of per-socket bandwidth, and 128 PCIe 6 lanes in single-socket configurations.
AMD positions Venice as a portfolio rather than a single SKU, spanning the SP7 socket (up to 256 cores), a smaller SP8 variant launching in 1H 2026 (8-128 cores), Venice-X with stacked cache in 2H 2027, and Verano, an AI-focused SP8 part with 24-channel LPDDR5X memory arriving in 2H 2026.
In benchmarks targeting agentic AI, networking, compilation and data-heavy workloads, AMD claims up to 3.4x throughput over Intel's Xeon 6980P and up to 1.7x over its own previous-gen Epyc 9965 in TPCx-AI testing. Using Nvidia's newly published SPEC CPU 2026 results for Vera, AMD also claims a 2.2x integer throughput lead with matched compiler settings.
For engineers, the numbers signal AMD's continued push on core density, cache capacity and memory bandwidth to strengthen its position against both Intel's incoming Xeon lineup and Nvidia's first server CPU efforts, though full SKU stacks and independent benchmarks are still pending.